Common Public Radio Interface (CPRI) v.5.0 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
- CPRI
- available
- CPRI v.5.0 Specifications 2…
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Common Public Radio Interface (CPRI) v.5.0 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
Common Public Radio Interface (CPRI) v.4.2 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
The DTS Adapter from Silvaco enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the debug/test capabili…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 contr…
V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz
V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
CAN Controller Core with 32/32 Message Objects
CANmodule-IIIx is a full functional CAN controller module that supports the concept of mailboxes.
AMBA AXI from ARM Holdings is an high performance on-chip bus architecture.
The MVD ASI Transmitter core is a drop-in module that includes the following functions : • 188 or 204 bytes MPEG-TS input • 8B/10…
The UDP/IP core is a drop-in module which includes its own MAC to send and receive UDP packets on an Ethernet Network.
10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)
INT 10012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Perfor…
10G TCP Offload Engine+MAC+Host_IF Very Low Latency (XTOE)
INT 10011 is the only SOC that integrates 10G TOE + 10 GEMAC + CPU interfaces in the smallest logic footprint.
V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the t…
Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the t…