I2C Controller IP – Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses or direct to/from Registers or Memory

The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or any Peripheral or CPU connecting through an internal AHB / APB / AXI / Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s).

The DB-I2C-S-Hs-Mode Controller implements the Slave-Transmit and Slave-Receive protocol according to the Philips I2C-Bus Specification, Version 2.1 as well as the updated NXP Rev 7 – 1 Oct 2021 Specification.

Figure 1 depicts the system view of the DB-I2C-S-Hs-Mode Slave Controller IP Core embedded within an ASIC, ASSP or FPGA device. The DB-I2C-S-Hs-Mode Controller receives and transmits data with respect to an external I2C Master Controller. The DB I2C-S-Hs-Mode can interface to a user Register Array, Memory such as SRAM, SDRAM, Flash, or a FIFO, or a Peripheral or CPU.

The DB-I2C-S-Hs-Mode IP Core can function standalone, without the requirement for an embedded processor.

• I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint:
  • Slave–Transmitter
  • Slave–Receiver
• Supports four I2C bus speeds:
  • Hs-Mode (3.4+ Mb/s)
  • Fast Mode Plus (1 Mbit/s)
  • Fast Mode (400 Kb/s)
  • Standard Mode (100 Kb/s)
• Digital Blocks optionally supplies a RTL Parameterized Register Array the user can use to construct their registers, or a Register Array / SDRAM / SRAM / Flash/ FIFO Interface the user can use to connect to their existing designs, or an AHB /APB / AXI / Avalon Master interface the user can connect Memory or Peripheralsto that are participating in the I2C transfer.
• DB-I2C-S-Hs-Mode Controller supports single register / memory access or burst access with address auto-increment capability.
• 7- or 10-bit addressing, General Call, SCL Low Wait States
• Enhanced SCL / SDA spike filtering capabilities
• 13 sources of internal interrupts with masking control
• Compliance with I2C specifications:
  • Compliance with AMBA AXI / AHB/ APB Protocol Specifications
  • Compliance with Avalon / Qsys Protocol Specifications
  • Philips – The I2C-Bus Specification, Version 2.1, January 2000
  • NXP Rev 7 – 1 Oct 2021
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASICdesign flows.

• The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core targets embedded applications where the I2C Slave Controller connects to a bank of registers and a block of Control & Status Register bytes must be transferred to or from the registers, or a memory device such as SDRAM / SRAM / FLASH / FIFO or an AHB / APB / AXI / Avalon Bus Peripheral must be interfaced to the I2C Bus. The DB-I2C-S IP Core functions standalone, without the requirement for an embedded processor.

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.