The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and…
- SPI / QSPI XSPI
- In Production
- Immediate
- Yes
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and…
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory.
LIN 2.2, 2.1 and 1.3 Protocol Controller IP
The LIN is a soft core of the Local Interconnect Network (LIN).
Used for controlling HDLC/SDLC transmission protocols
The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol.
CAN 2.0 & CAN FD Bus Controller IP
The CAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial app…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.4 specification.
HDMI 1.3 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification.
HDMI 1.3 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification.
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55LP
HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification.
HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' produ…
Rail to rail LVDS receiver 1 Gbps
LVDS_RX is LVDS receiver with rail to rail input range.
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the tr…
ISO/EIC 7816 and EMV4.3 UART, with protocol controller and timers
The ISO7816 UART contains all of the digital logic necessary to communicate with an ISO/IEC 7816 or EMV 4.3 integrated circuit ca…
Four-Wire slave IP for use with the Mentor M8051W and M8051EW
The M4WIS adds four-wire slave capability to the M8051W and M8051EW microcontroller designs that are compatible with the I2C Fast…
Two-Wire slave IP for use with the Mentor M8051W and M8051EW
The M2WIS adds two-wire slave capability to M8051W and M8051EW designs.
Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006.
SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfe…
DO-254 AXI to PCI Bridge 1.00a
Provides full bridge functionality between the Xilinx® AXI interface and a 32-bit Revision 2.2 compliant Peripheral Component Int…
DO-254 AXI Bridge For PCI Express 1.00a
An interface between the AXI4 and PCI Express®.
DO-254 Tri-Mode Ethernet Media Access Controller (TEMAC) 1.00a
Consists of a separate transceiver (transmitter) and receiver IP core implementing a point to multipoint communication channel bu…