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Vendor:
Syntill8 Ltd.
Category:
Ethernet
UDP Network Interface with Ethernet MAC for the M8051W & M8051EW
The UDPMAC implements a UDP transport layer, and IP layer functions, compatible with the RFC768 and RFC791 protocols.
Overview
The UDPMAC implements a UDP transport layer, and IP layer functions, compatible with the RFC768 and RFC791 protocols.
The UDPMAC also includes Ethernet Media Access Controller (MAC) functionality that is compatible with the RFC894 protocol. The MAC interfaces to an external PHY using the four-wire RGMII gigabit interface. The PHY can be controlled using the UDPMAC via a four-wire MDIO interface.
The integral ARP protocol handler enables the UDPMAC to autonomously identify itself on networks and respond to ARP MAC address requests. The ARP logic includes a single-depth cache suitable for identifying the remote device on a point-to-point connection.
The UDPMAC also includes Ethernet Media Access Controller (MAC) functionality that is compatible with the RFC894 protocol. The MAC interfaces to an external PHY using the four-wire RGMII gigabit interface. The PHY can be controlled using the UDPMAC via a four-wire MDIO interface.
The integral ARP protocol handler enables the UDPMAC to autonomously identify itself on networks and respond to ARP MAC address requests. The ARP logic includes a single-depth cache suitable for identifying the remote device on a point-to-point connection.
Key features
- Simple IP datagram interface providing transport–level exchange of data over IP networks
- Compatible with the RFC768 UDP specification
- Includes a simple ARP protocol handler, suitable for point-to-point connections to switches
- An RFC894 compatible Ethernet MAC
- Integral MDIO controller interfaces to external PHY devices using a 1 gigabit RGMII interface
- Programmable MAC, IP and port addresses
- DMA controller automates data transfers between network and host data memory, interrupt and SFR buses with no additional glue logic required
- Integral transmit and receive data FIFOs minimise the processor overhead required to service the link
- Supports DMA, interrupt-driven and polled data transfers
- Asynchronous data FIFOs enable host clock to operate asynchronously to the PHY clock
- Optional clock prescaler minimises power consumption while active
- Rests in power saving mode when the interface is not enabled
- Wake up on MAC address, or IP address match, can be used to cold start a M8051W and M8051EW microcontroller, in addition to interrupt driven wake ups
- Binds tightly to M8051W and M8051EW external data buses
Block Diagram
UDPMAC - 265944 block diagram
Benefits
- The UDPMAC adds IP networking capability to the M8051W and M8051EW IP designs. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC SoC and FPGA designs.
What’s Included?
- VHDL '93 and Verilog 2001 RTL source code
- VDL and Verilog functional demonstration testbench
- Demonstration assembler code
- Simulation scripts for Modelsim and Cadence
- Synopsys synthesis compile scripts and SDC timing constraint files
- Example Mentor DFT and ATPG scripts
- Example netlist implementation with SDF files
- Detailed product specification and a user guide containing implementation notes
Specifications
Identity
Part Number
UDPMAC - 265944
Vendor
Syntill8 Ltd.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United Kingdom
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Frequently asked questions about Ethernet IP cores
What is UDP Network Interface with Ethernet MAC for the M8051W & M8051EW?
UDP Network Interface with Ethernet MAC for the M8051W & M8051EW is a Ethernet IP core from Syntill8 Ltd. listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.