Vendor:
Microtronix Datacom Ltd.
Category:
Video Transport
Camera Link Transceiver
The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Link™ communication …
Overview
The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Link™ communication interfaces including Base, Medium & Full Channel Link configurations. The core supports camera control signals, serial communication, and video data. It is designed for building both Camera and Frame Grabber devices.
The Camera Link standard is based on Channel Link® technology developed by National Semiconductor. Channel Link uses LVDS technology for transmitting digital data using a parallel-to-serial transmitter and a serial-to parallel-receiver to transmit data at rates up to 2.38 Gbps. The base Channel Link standard uses 28 bits to represent up to 24 bits of pixel data and 3 bits for Video Sync signals. These consist of Data Valid, Frame Valid, and Line Valid bits. The data is serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The Receiver accepts the four LVDS data streams and one LVDS clock, and then deserializes the data into 28 bits of parallel data and a clock.
The Camera Link standard is based on Channel Link® technology developed by National Semiconductor. Channel Link uses LVDS technology for transmitting digital data using a parallel-to-serial transmitter and a serial-to parallel-receiver to transmit data at rates up to 2.38 Gbps. The base Channel Link standard uses 28 bits to represent up to 24 bits of pixel data and 3 bits for Video Sync signals. These consist of Data Valid, Frame Valid, and Line Valid bits. The data is serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The Receiver accepts the four LVDS data streams and one LVDS clock, and then deserializes the data into 28 bits of parallel data and a clock.
Key features
- Supports 8-bit, 10-tap Base, Medium & Full Camera Link interfaces
- Supports 64-bit and 80-bit extended Full configurations
- Camera and Frame Grabber configurations
- 7:1 Camera Link Serializer/Deserializer (SerDes)
- Transmission clock rates to 85 MHz. in Cyclone, Stratix & Arria devices
- Auto Link alignment of Medium and Full Camera Link sources
- Power Over Camera Link (PoCL) SafePower
- Bi-directional serial Camera Link communication
- Configuration GUI streamlines design process
- Supports: Cyclone II, III, IV, Arria II GX, & Stratix III, IV devices
Block Diagram
1600861 block diagram
Applications
- The Camera Link Transceiver IP Core is specifically targeted at industrial video applications including; industrial vision systems, high-speed video interconnects, Camera Link frame grabber devices, interface conversion, and video processing equipment.
What’s Included?
- The IP is supplied as an FTP download. It includes:
- Java Configuration GUI
- TimeQuest timing analyzer Synopsis Design Constraint (SDC) file
- VHDL ModelSim library
- User documentation
- Quartus Reference Design supporting a Camera Link Base, Medium & Full configurations
- Includes perpetual IP core license with 1 year of updates
- A 30-day Altera OpenCore Plus evaluation license available. (Use the request link above.)
Specifications
Identity
Part Number
1600861
Vendor
Microtronix Datacom Ltd.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Canada
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Frequently asked questions about Video Transport IP cores
What is Camera Link Transceiver?
Camera Link Transceiver is a Video Transport IP core from Microtronix Datacom Ltd. listed on Semi IP Hub.
How should engineers evaluate this Video Transport?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.