Vendor: SOC-E Category: IEEE-1588 / PTP

IRIG 200-04 compliant slave

IRIG 200-04 compliant time synchronization slave / time receiver for FPGA

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Overview

ITS is an IRIG 200-04 compliant time synchronization slave / time receiver for FPGA. This IRIG-B slave / time receiver IP has been designed to support multiple IRIG-B coded expressions as well as DCLS modulation in order to provide maximum flexibility.

ITS can be configured to support the most extended IRIG-B time codes to provide higher compatibility with the majority of IRIG-B masters / time transmitters in the market. This configuration can be done before implementing the IP by selecting the desired modulation type, carrier frequency, coded expression and other parameters in the FPGA design tool as well as during runtime using register based configuration.

It has been designed as a hardware-only (VHDL) IP Core. No microprocessor or software is required in order to reduce integration complexity.

Key features

Time Synchronization

  • IRIG 200-04 compliant time synchronization slave
  • Support for DCLS modulation
  • Input type (IRIG-B time code) configurable both before implementation and on the fly
  • Sub-microsecond synchronization with the IRIG-B master
  • 64-bit internal timer synchronized in time and frequency with the IRIG-B master
    • 32-bit for timestamp in seconds and 32-bit for nanoseconds

Management & Monitoring

  • AXI4-Lite or UART management interfaces to access control registers (selectable at synthesis time)

Benefits

  • Multiple Time Code Support: Including year information, control functions and straight binary seconds.
  • PPS and 10MHz Inputs Available: For synchronizing to high precision external clocks.
  • IEEE1344 Extension Supported
  • Fast & Smooth Integration: GUI available for FPGA vendor tools (i.e., AMD Vivado™ Design Suite).
  • Evaluation Version Available: Encrypted, time-limited version available.

What’s Included?

Technical Support

IP Licenses are provided along with a Technical Support package that ensures a direct communication channel with our highly experienced support engineers. This is vastly valued during customer product development & integration phases.

Verification

All our IP Cores are rigorously tested, hardware-validated and verified in real-life environments. A 3-phase based IP product verification is applied:

  • Entity/Block-oriented simulation
  • Global-oriented simulation
  • In-hardware validation

Deliverables

  • Encrypted/Source RTL code
  • Documentation (IP Core datasheet)
  • (Optional) AMD Vivado™ design suite example design

Specifications

Identity

Part Number
ITS
Vendor
SOC-E
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SOC-E
HQ: Spain
Contact SOC-E

Learn more about IEEE-1588 / PTP IP core

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Frequently asked questions about Time Synchronization IP cores

What is IRIG 200-04 compliant slave?

IRIG 200-04 compliant slave is a IEEE-1588 / PTP IP core from SOC-E listed on Semi IP Hub.

How should engineers evaluate this IEEE-1588 / PTP?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this IEEE-1588 / PTP IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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