Vendor: Roa Logic BV Category: Bus Fabric

AHB-Lite General Purpose Memory Module

The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Mas…

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Overview

The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defined in the AMBA 3 AHB-Lite v1.0 specifications are fully supported.

The IP supports a single AHB-Lite based host connection and enables address & data widths, memory depth & target technology to be specified via parameters. An option to register the memory output is also provided.

Key features

  • Full support for AMBA 3 AHB-Lite protocol
  • Fully parameterized
  • User-defined address and byte-aligned data widths supported
  • Configurable memory depth, limited only by target technology capability
  • Technology-specific memory cells instantiated automatically
  • Combinatorial or registered data output

Block Diagram

AHB-Lite Memory block diagram

Benefits

  • Design to support any silicon technology

What’s Included?

  • Full Source Code
  • Testbenches
  • Compilation Scripts
  • Documentation

Specifications

Identity

Part Number
AHB-Lite Memory
Vendor
Roa Logic BV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Roa Logic BV
HQ: The Netherlands
Contact Roa Logic BV

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Frequently asked questions about On-Chip Bus IP cores

What is AHB-Lite General Purpose Memory Module?

AHB-Lite General Purpose Memory Module is a Bus Fabric IP core from Roa Logic BV listed on Semi IP Hub.

How should engineers evaluate this Bus Fabric?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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