Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

112G-VSR PAM4 SerDes PHY

PPA optimized for short reach connectivity

PHY TSMC 7nm N7+ Silicon Proven View all specifications

Overview

Industry-Leading Power Optimized 112G-VSR PAM4 SerDes PHY Solution

In data center interconnects, short-reach connectivity is needed in use-case scenarios for chip-to-chip, chip-to-optical-module, near-packaged optics, co-packaged optics or die-to-die. Power and area efficiency is critical in these use cases. The Cadence 112G-VSR PAM4 SerDes PHY provides optimized power, performance, and area (PPA) for short-reach to medium-reach applications at 1.25Gbps to 116Gbps data rates.

Key features

Optimized Power, Performance, and Area for Short-Reach Applications

  • 1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
  • Power optimized for short-reach applications with configurability
  • Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
  • Beachfront optimized floorplan allows north-south and east-west SoC edge placement
  • Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
  • Enables 800Gbps networking with PHY and Controller solutions

Block Diagram

112G-VSR PAM4 SerDes PHY block diagram

Benefits

Enable Short Reach and Optical I/O Connectivity

  • Superior Power Efficiency: Ultra-low power optimized for short-reach applications and optical I/O
  • Robust Performance: Mature DSP-based architecture providing extra performance margin beyond short-reach standard requirements
  • Flexible Data Rates: 1.25Gbps to 116Gbps flexible data rates supporting ETH, OTN, CPRI, JESD, and proprietary protocol rates
  • Standard Compliance: Compliant with IEEE802.3 and OIF 112G short-reach standards

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Silicon Proven

Specifications

Identity

Part Number
112G-VSR PAM4 SerDes PHY
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about Single-Protocol PHY IP

What is 112G-VSR PAM4 SerDes PHY?

112G-VSR PAM4 SerDes PHY is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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