Vendor: Actt Category: MIPI PHY

1.5G MIPI D-PHY in SMIC 130nm~28nm

The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.

Contact Provider Request Datasheet
MIPI D-PHY SMIC 130nm G Available on request View all specifications

Overview

The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specification for MIPI D-PHY rev1.1 with speeds up to 1.5 Gbps per lane in 0.11um G process node, this ACTT Design IP of MIPI D-PHY supports DSI/DSI-2 and CSI-2 protocols.
These IPs is a mixed-signal PHY consisting of a DSI D-PHY transmitter and a DSI D-PHY receiver. The PHY IP is designed to be robust under varying signal strength and noise conditions.
The PHY IP is part of the comprehensive ACTT Design IP portfolio comprised of high speed interface, memory, low power analog, and system IPs.

Key features

  • ? Compliant with MIPI D-PHY v1.1 (Max speed 1.2/1.5 Gbps per lane)
  • ? Scalable up to 4.8 (6) Gbps in 4 data lanes
  • ? Low-power escape modes, ULPS and contention detection
  • ? 8-bit PHY Protocol interface (PPI)
  • ? Matched analog design for low inter-lane skew
  • ? Automatic termination control in high-speed and low-power modes
  • ? shutdown mode
  • ? Integrated BIST capable of producing and checking PRBS
  • ? Automatic termination control in high-speed and low-power modes
  • ? Compact footprint and low-power dissipation
  • ? Attachable PLL for master applications
  • ? Extensive access to internal programmability register
  • ? Master, slave, Tx and Rx-only configurations
  • ? 50% DDR output clock duty cycle

Benefits

  • ? Fully compliant with MIPI D-PHY v1.1 spec
  • ? Support MIPI DSI (v1.1/v1.2/v1.3) protocol
  • ? Support HS TX/RX data rate up to 1.2Gbs (up to 1.5Gbs upon request) per lane
  • ? Support LS TX/RX data rate up to 10Mbps and Ultra low power mode
  • ? Support TX/RX physical 1C2D (data lane scalable to 1,2 lanes) or 1C4D layout, data lanes scalable to 1,2,3,4 lanes)
  • ? Bi-directional data lane 0 turnaround
  • ? Support contention detect errors and detecting protocol errors
  • ? 8 bits PPI Interface, support DSI/DSI-2 specifications to MIPI DSI controller
  • ? Integrated BIST capable of producing or checking PRBS in test mode

Applications

  • DSI/DSI-2 Host
  • CSI Host (suggest use ACTT pure CSI D-PHY)
  • DSI/DSI-2 Device
  • CSI-2 Device (suggest use ACTT pure CSI D-PHY)

Silicon Options

Foundry Node Process Maturity
SMIC 130nm G Available on request

Specifications

Identity

Part Number
1.5G MIPI D-PHY in SMIC 130nm~28nm
Vendor
Actt
Type
Silicon IP

Standards & Interfaces

MIPI PHY
MIPI D-PHY

Provider

Actt
HQ: China
Contact Actt

Learn more about MIPI PHY IP core

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Frequently asked questions about MIPI PHY IP

What is 1.5G MIPI D-PHY in SMIC 130nm~28nm?

1.5G MIPI D-PHY in SMIC 130nm~28nm is a MIPI PHY IP core from Actt listed on Semi IP Hub. It is listed with support for smic Available on request.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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