Vendor: T2M GmbH Category: Multi-Protocol PHY

PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm

The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design.

TSMC 7nm N7+ In Production View all specifications

Overview

The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design. A full variety of PCIe 4.0 Base applications are supported by the PCIe 4.0 IP, which also complies with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support PCIe 4.0 traffic at 16Gbps. It is backward compatible with data rates of 2.5Gbps, 5.0Gbps, and 8.0Gbps for PCIe 3.1, PCIe 2.1, and PCIe 1.1, respectively. The PCIe 4.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalization methods.

Key features

  • Compliant with PCIe 4.0 Base Specification
  • Compliant with PIPE 4.4
  • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
  • Supported physical lane width: x4
  • Supported parallel interface: 32-bit
  • Supported input reference clock: 100 MHz
  • Supported parallel interface data clock: 62.5 MHz, 125 MHz and 250 MHz and 500MHz
  • Supporting low power operation with configurable setting in power state P1/P2/L1 PM Substates: PLL control, reference clock control, and embedded power gating control
  • Silicon proven in TSMC 7nm
  • Operating Voltage: 0.8V and 1.2V
  • Providing robust testability by low-cost Build-In Self-Test (BIST) via near-end analog and external loopback interface as well as far-end analog/digital loopback interface

Block Diagram

PCIe 4.0 Serdes PHY IP in 7nm block diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ In Production

Specifications

Identity

Part Number
PCIe 4.0 Serdes PHY IP in 7nm
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Multi-Protocol PHY IP core

Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm?

PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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