Overview
For high-bandwidth applications, the PCIe 5.0 PHY IP offers excellent performance, multi-lane capabilities, and low power design. The PCIe 5.0 IP complies with the PIPE 5.2 standard and supports the whole spectrum of PCIe 5.0 Base applications. High-speed mixed-signal circuits are included into the IP to accommodate 32Gbps PCIe 5.0 traffic.
The PCIe4.0 data rate at 16 Gbps, the PCIe 3.1 data rate at 8.0 Gbps, the PCIe 2.1 data rate at 5.0 Gbps, and the PCIe data rate at 2.5 Gbps are all backward compatible with this device. The needs for various channel conditions may be met by the PCIe 5.0 IP thanks to its support for both TX and RX equalization methods.
Learn more about Multi-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
