Vendor: T2M GmbH Category: Multi-Protocol PHY

LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL

The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consu…

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SMIC 40nm LL In Production View all specifications

Overview

The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, LVDS or MIPI DSI system. For GVI/LVDS system, Macro consists of multi-transmitter channels and one SU unit. The speed of transmitter macro is up to 4.0Gbps and can be configured to GVI (CML) or LVDS mode. For MIPI DSI system, a DSI configuration includes a Clock Lane Module and four Data Lane Modules.

Key features

  • GVI
  • Support data rate: 0.5Gbps~4.0Gbps
  • configurable reference clock frequency
  • Per-lane 10-bit/9-bit/8-bit/7-bit parallel interface
  • Support Spread Spectrum clock generation: up to
  • ±5000ppm@31.5KHz
  • AC coupling, 75nF~200nF at both ends and one end in TX near-end.
  • One shared PLL for all lanes
  • Individually power down for each lane
  • Support 0~9dB programmable 2-tap FFE (Feed forward equalization)
  • LVDS
  • Support data rate: 0.25Gbps~2.0Gbps
  • Configurable reference clock frequency
  • Per-lane 10-bit/9-bit/8-bit/7-bit parallel interface
  • DC coupling
  • One shared PLL for all lanes
  • Individually power down for each lane
  • Support 0~9dB programmable 2-tap FFE (Feed forward equalization)
  • DSI
  • One Clock Lane Channel and four Data Channels
  • Data Channel 0 : Bi-directional with Low-Power RX (LP-RX) and Low-Power CD (LP-CD)
  • Channel 1-4: High-Speed TX (HS-TX) and a Low-Power TX (LP-TX)
  • HS operation rate : 187.5Mbps~1.5Gbps
  • LP operation rate: 10Mbps
  • DC Coupling
  • One shared PLL for all lanes
  • Contention detection module
  • Common Features
  • Embedded BIST
  • Support wire bonding package
  • Reliability
  • Life Time : 20 years, with average temperature up to 100degC : 10 years, with average temperature up to 110degC
  • Availability : 100%
  • ESD(HBM) : over 2000V
  • ESD(CDM) : over 500V
  • Latch-up : >100mA

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
SMIC 40nm LL In Production

Specifications

Identity

Part Number
MIPI D-PHY/LVDS Tx Combo PHY IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

Learn more about Multi-Protocol PHY IP core

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Frequently asked questions about Multi-Protocol PHY IP cores

What is LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL?

LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for smic In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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