Vendor: T2M GmbH Category: Single-Protocol PHY

USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF

The USB 3.2 Gen2X1 transceiver IP offers all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.

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PHY USB 3.2 TSMC 7nm N7FF Available on request View all specifications

Overview

The USB 3.2 Gen2X1 transceiver IP offers all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps. Both the UTMI+ and PIPE4.0 specifications are met by it. The USB 3.2 Gen2X1 IP includes high-speed mixed signal circuits to enable Gen2 and Gen1 traffic and is backward compatible to high-speed data rates at 480Mbps, full-speed data rates at 12Mbps, and low-speed data rates at 1.5Mbps. The USB 3.2 Gen2X1 IP incorporates an active switch to support bi-directional plug-in and particular functionalities (such as VBUS configuration and USB attachment cable orientation detection) through the CC1/CC2 pins specified in the Type-C connection in order to support the USB Type-C connector.

Key features

  • Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
  • Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
  • Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
  • Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
  • Integrates an active switch to support the orientation-less connection with USB Type-C connector
  • Provides an auxiliary CC module IP to support USB Type-C related functions
  • Supports both wire-bond and flip-chip package type
  • Silicon Proven in TSMC 7FF

Block Diagram

USB 3.2 Gen2 PHY IP in 7FF block diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7FF Available on request

Specifications

Identity

Part Number
USB 3.2 Gen2 PHY IP in 7FF
Vendor
T2M GmbH
Type
Silicon IP
Controller / PHY
PHY

Standards & Interfaces

Supported Standards
USB 3.2

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

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Frequently asked questions about Single-Protocol PHY IP

What is USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF?

USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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