Integrating SpaceWire and SpaceFibre for Space Communication
Fabio Malatesta, Frontgrade Gaisler
Vendor:
Frontgrade Gaisler
Category:
Spacewire
SpaceWire CODEC
The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.
Overview
The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).
Data is transmitted and received through 9-bit wide FIFOs with configurable depth. The core also provides an interface for transmitting and receiving Time-codes as well as configuring the link properties such as the link rate.
For critical space applications, a fault-tolerant (FT) version of GRSPW_CODEC is available with full SEU protection of all RAM blocks.
Key features
- Full implementation of SpaceWire standard (ECCS-E-ST-50-12C)
- Simple 9-bit wide FIFO host interface
- Redundant port
- SEU protection fault-tolerance
Block Diagram
GRSPW_CODEC block diagram
Benefits
- Tested and verified against several other SpaceWire cores
- High frequency
- Easily portable between FPGA and ASIC
- Low-cost project license
- SEU protection of all RAM blocks
What’s Included?
- Encrypted RTL
- Stand-alone testbench
- User's manual
Specifications
Identity
Part Number
GRSPW_CODEC
Vendor
Frontgrade Gaisler
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Frontgrade Gaisler
HQ:
Sweden
Cobham Gaisler provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. The key product is the LEON synthesizable processor model together with a full development environment and a library of IP cores (GRLIB). Our personnel have extended design experience, and have been involved in establishing European standards for ASIC and FPGA development. Aeroflex Gaisler has a long experience in the management of ASIC development projects, and in the design of flight quality microelectronic devices. The company specializes in digital hardware design (ASIC/FPGA) for both commercial and aerospace applications.
Learn more about Spacewire IP core
Time Sensitive Networking for Aerospace
This white paper highlights the integration of Time-Sensitive Networking (TSN) in the aerospace industry. It provides an overview of TSN standards and profiles and the IEEE P802.1DP standard relevant to aerospace applications. It also discusses key topics such as time synchronization, latency, resource management, and reliability in the context of TSN.
Frequently asked questions about SpaceWire IP cores
What is SpaceWire CODEC?
SpaceWire CODEC is a Spacewire IP core from Frontgrade Gaisler listed on Semi IP Hub.
How should engineers evaluate this Spacewire?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Spacewire IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.