Gigabit Ethernet with IEEE 1588 and AVB

The Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and supports protocol extensions for Audio Video Bridging (AVB). The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Media Independent Interface (GMII). It also supports optional Reduced MII (RGMII), and Serial GMII (SGMII). The Gigabit Ethernet IP also implements Hardware-assisted 1588 Protocol for Time stamping the Receive and Transmit PTP Packets.

The Gigabit Ethernet with IEEE 1538 MAC IP is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers, and Ethernet adapter cards. The Gigabit Ethernet IP supports half-duplex mode at 10/100 Mbps and full-duplex mode at 10/100/1000 Mbps. The Gigabit Ethernet IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. A processor bus master and a 32-bit scatter-gather DMA transfer packets between the internal FIFOs and the host memory to enhance system performance.

The Gigabit Ethernet with IEEE1538 MAC IP supports 4-bit MII based 10/100 Mbps PHY and 8-bit GMII based 10/100/1000 Mbps PHY. An MDIO/MDC (Management Data Input/Output and Management Data Clock) management interface provides control and management functions to external PHY devices. The Gigabit Ethernet IP also provides enhanced programmable features for minimizing application complexity and pre/post message processing.

The Gigabit Ethernet IP supports MIB, SNMP, RMON, VLAN Q-Tag frame, and Jumbo frames. It also includes dynamic generation, checking, and stripping of FCS field, automatic pad field insertion, automatic retransmission and detection of collision frames, collision avoidance and handling. Other features of the Gigabit Ethernet IEEE1538 MAC IP include generation and decoding of PAUSE control frames, frame boundary delimitation, frame synchronization, and error detection.

• Hardware Assisted 1588 V1/V2 Support
• Full-duplex mode at 10/100/1000 Mbps
• Half-duplex mode at 10/100 Mbps
• Supports IEEE 802.3-2008 compliant MII, RMII, SMII, GMII, RGMII, and SGMII
• Independent 32-bit scatter-gather DMA with big/ little endian operation
• Optional VLAN Q-Tag frame support
• CSMA/CD Protocol for half-duplex mode
• PAUSE frame based flow control in full-duplex mode
• MDIO/MDC management interface
• 802.3 compliant MIB, SNMP, RMON management support
• Configurable transmit and receive FIFOs
• Supports Jumbo frames
• Supports magic packet and Wake-Up frames
• Optional AXI, AHB, PCIe, PCI or custom bus interface

• Fully compliant core
• Premier direct support from Arasan IP core designers
• Easy-to-use industry standard test environment
• Un-encrypted source code allows easy implementation
• Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured

• RMM Compliant Synthesizable RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents