Vendor: M31 Technology Corp. Category: Single-Protocol PHY

Display Port 2-Lane Transmitter PHY

M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.

Overview


M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supports 20Gbps UHBR20, 13.5Gbps UHBR13.5, 10Gbps UHBR10, 8.1Gbps HBR3, 5.4Gbps HBR2, 2.7Gbps HBR and 1.62Gbps RBR data rates. Additionally, the IP also includes the transceiver for the AUX channel.

Key features

  • Supports 1.62G to 20Gbps data rates and compact die area
  • Supports x1, x2 and x4 lanes
  • Supports post-cursor 1 FFE for Main Link transmitter
  • Supports four swing levels for Main Link transmitter
  • Supports four pre-emphasis levels for Main Link transmitter
  • Supports 20-bit/40-bit databus width of parallel interface
  • Supports PLL-alive mode
  • Supports built-in internal loopback mode for testing
  • Supports AUX channel feature
  • Supports Wire-Bond or Flip-Chip packages
  • Can be integrated with USB PHY to realize type-C DP alternate

Specifications

Identity

Part Number
M31 DisplayPort TX IP
Vendor
M31 Technology Corp.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is Display Port 2-Lane Transmitter PHY?

Display Port 2-Lane Transmitter PHY is a Single-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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