ChipScope Pro (IBERT) for Virtex-6 FPGA GTH
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
- Test / Debug
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
ChipScope Pro (IBERT) for Virtex-6 FPGA GTH
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
The AXI VIP can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design f…
AXI Stream Verification IP (VIP)
The AXI Stream VIP can be used to verify connectivity and basic functionality of AXI Stream masters and AXI Stream slaves with th…
AXI Sideband Formatter Utility
The Xilinx® LogiCORE™ AXI Sideband Formatter Utility is used to insert and recover sideband information onto the AXI USER signals…
The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to…
Converts Avalon Master Endpoints to AXI for seamless interconnection and integration
Xilinx provides an 100M/1G TSN Subsystem to accelerate time to market and drive the convergence of low latency deterministic Indu…
1G/10G/25G Switching Ethernet Subsystem
The 1G and 10G Switching Ethernet Subsystem dynamically switches an Ethernet Media Access Controller (MAC) between 1G or 10G phys…
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TSN Ethernet Endpoint Controller
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time …
Video transfer over IP, Supports PTP SMPTE ST 2059 is a standard for synchronization of video equipment over an IP network.
TRC6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…
Dual Serial ATA 1.5/3.0/6.0 Gbps Phy
TRC6002CSA is a Dual Serial ATA (SATA) Host PHY core for interfacing serial data between Storage Device and external 2-port PHY.
MIPI SPMI Controller or Target
The SPMI-CTRL core implements a featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus.
xSPI, HyperBus™, and Xccela™ Serial Memory Controller
The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memo…
MIPI C-PHY/D-PHY Combo v1.2 IP in TSMC(5nm, 7nm, 12/16nm, 28nm and 40nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.