Gigabit Ethernet PHY
- Single-Protocol PHY
- Silicon Proven
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Gigabit Ethernet PHY
SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
M31 Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
10/100 Ethernet PHY for TSMC 22nm ULP
10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver.
Low-Latency 10/100/1000 Ethernet MAC
The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.…
200G / 100G / 40G / 25G / 10G / 1G TCP Offloading Engine
The TCP Offloading Engine IP core (TOE200G/100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU.
USB3.0/PCIe2.0 Combo PHY in TSMC28HPC+
USB3PCIE20T28HPCP is a USB3.0 and PCIe 2.0 Combo PHY IP solutoin designed for a mobile and data consumer applications in T28nm pr…
Gigabit Ethernet PHY (in production)
Primeexpress PCIE Gen5 digital controller from Primesoc, is well architect,high performance, modular designed and tailor made to …
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V1.0/V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v1.0 and D-PHY v1.2”, which consists of Bi-directional 1-Clock a…
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Slave V1.0/V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v1.0 and D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
Multi Protocol Synchronous Serial Engine IP
The developed IP integrates basic serial interface protocols like UART, SPI and I2C into a single AXI interface port.
General Video Interface HS Receiver PHY
IP
General Video Interface HS Transmitter PHY
IP
Parallel to Serial Converter, 8b, Fmax 600MHz - XFAB 180nm
Parallel to Serial Converter, 8b, Fmax 600MHz - XFAB 180nm
SPI and Efuse - GlobalFoundries 130nm RFSOI
SPI and Efuse - GlobalFoundries 130nm RFSOI
1G Deep Buffering Memory Ethernet Switch IP Core
switch supporting buffering of large amounts of data in external DDR RAM The 1G deep buffering memory Ethernet Switch is an Ether…
The PCI-T32 implements a target PCI interface compliant with the PCI 2.3 specification.
AVB/Automotive Ethernet Switch
The demand for higher bandwidth in the car is growing quickly.
CAN FD controller compatible with both CAN 2.0 and CAN FD
GRCANFD is a CAN IP core implementing a CAN-FD controller compatible with both CAN 2.0 and CAN FD.
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver.