Vendor: Xilinx, Inc. Category: PCI Express

QDMA Subsystem for PCI Express

The Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with th…

Contact Provider Request Datasheet

Overview

The Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block.  The IP provides an optional AXI4-MM or AXI4-Stream user interface.

The QDMA solution provides support for multiple Physical/ Virtual Functions with scalable queues, and is ideal for applications that require small packet performance at low latency.

The QDMA solution is available for early access beta customers in 2018.1 (April, 2018). 

Key features

  • Supports 64, 128, 256 and 512-bit data path
  • Supports x1, x2, x4, x8, or x16 link widths.
  • Supports Gen1, Gen2, and Gen3 link speeds
  • Support for both the AXI4-Memory Mapped and AXI4-Stream interfaces per queue
  • 2K queue sets
    • 2K H2C Descriptor rings
    • 2K C2H Descriptor rings
    • 2K C2H Write back rings
  • Supports Polling Mode (Status Descriptor Write Back)
  • C2H Stream interrupt moderation
  • C2H stream CMPT entry coalesce
  • Descriptor and DMA Customization through user logic
    • Allow Custom Descriptor format
    • Traffic Management
  • Supports SR-IOV up to 4 Physical Functions and 252 Virtual Functions
    • Thin Hypervisor model
    • Allows only privileged/Physical function (PF) to program contexts and registers
    • Function Level Reset support
    • Mailbox
  • Interrupts
    • 2K MSI-X vectors
    • Up to 8 MSI-X per function
    • Interrupt coalescing

Specifications

Identity

Part Number
QDMA Subsystem for PCI Express
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

Learn more about PCI Express IP core

How to design FPGA-based advanced PCI Express endpoint solutions

Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, enterprise, mobile, workstation, networking, communica

Repeatable results with design preservation

Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well. The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations.

Frequently asked questions about PCIe IP cores

What is QDMA Subsystem for PCI Express?

QDMA Subsystem for PCI Express is a PCI Express IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP