The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
- PCIe 6.0
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
The HDMI Rx PHY is the physical layer of an HDMI receiver.
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application.
This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX).
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-h…
CXL Controller (Spec Version 2.0 and Below)
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
The vendor provides designers with configurable USB4 Controller and Router IP.
PCIe 6.0 PHY G2 , SS SF4X x4, North/South (vertical) poly orientation
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
USB-C 3.2 DP/TX PHY ebdaux in Samsung (SF4X, SF4E, SF2)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controll…
TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC packaging solutions, Integrated Fan-Out (InF…
UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
<4Gbps Low Power D2D Interface in TSMC 16nm & 28nm
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Custom die-to-die interface in 12/16nm process technology.
112G LRM PHY, TSMC N5 x2, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutio…
The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices.
PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …