Logic Fruit Technologies has developed an ARINC 818-3 Transmitter & Receiver IP Core, supporting line rates up to 28 Gbps.
- Video Transport
- Get in touch with us.
- DO-254, CEMILAC certificati…
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Logic Fruit Technologies has developed an ARINC 818-3 Transmitter & Receiver IP Core, supporting line rates up to 28 Gbps.
Highest performance Six-wide, RVA23, CHI bridge, RAS Functionality, Scalable to 256 cores
The highest performance P870-D is targeted for datacenter applications which benefit from parallelism, including storage, web ser…
DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
CSI-2 RX IP supports both C-PHY v1.2 and D-PHY v2.0 interfaces, enabling flexible integration across a wide range of image sensor…
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The DSC Encoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
UCIe Controller baseline for Streaming Protocols
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
112G PHY, TSMC N5 x2, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.
Two-Digit Nanosecond PCIe 7.0-CXL 4.0 Link Controller IP
The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with glob…
MIL-STD-1553B is a military specification for a Digital Time Division Command/Response Data Bus, featuring half-duplex, Mancheste…
The DP and eDP TX/RX PHY IP provides a compact, low-power solution for high-speed external display interfaces.
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and ot…
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs.
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semicondu…
Peripheral Bus (APB) is one of the Microcontroller Bus Architecture (AMBA) family protocols.
DisplayPort 1.2a TX PHY targeting 28nm Artix-7
DisplayPort 1.2a compatible AMD/Xilinx hardware specific Hardware proven on AMD/Xilinx 28nm FPGA fabric Fabric: 28nm Artix-7 Tran…
112G VSR PHY, TSMC N5 x2, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…