eUSB2 v1.1 Dual-Role, repeater/native mode PHY, TSMC N5, 1.2V, N/S orientation
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
- Single-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
eUSB2 v1.1 Dual-Role, repeater/native mode PHY, TSMC N5, 1.2V, N/S orientation
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
USB1.1 FS/LS PHY, TSMC 55ULP_EF
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
USB1.1 FS/LS PHY, TSMC 40ULP_EF
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
USB2.0 Dual-Role PHY, SMIC 55LL
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, SMIC 40LL
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, UMC 28HPC+, N/S orientation
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, TSMC 55EF
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
The PCIe Gen4.0 PHY IP offers a low-power, compact solution with proven performance and robust signal and power integrity, making…
The PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations.
Logic Fruit Technologies has developed an ARINC 818-3 Transmitter & Receiver IP Core, supporting line rates up to 28 Gbps.
Highest performance Six-wide, RVA23, CHI bridge, RAS Functionality, Scalable to 256 cores
The highest performance P870-D is targeted for datacenter applications which benefit from parallelism, including storage, web ser…
DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
CSI-2 RX IP supports both C-PHY v1.2 and D-PHY v2.0 interfaces, enabling flexible integration across a wide range of image sensor…
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The DSC Encoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…