Vendor: Qualitas Semiconductor Category: Multi-Protocol PHY

PCIe Gen5/6 PHY IP

The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with glob…

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Overview

The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with global partners,

Built on advanced FinFET process nodes, the IPs incorporate DSP-based equalization, low latency, and industry-proven interoperability—making them ideal for PCIe 6.0 and CXL-ready systems.

Key features

  • Best-in-class Power / Performance / Area competitiveness
  • Compliant to PCIe 5.0/6.x Base specification
  • Supports lane configurations according to the customer’s demands
  • Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32GT/s and 64GT/s (PAM4)
  • Supports power-down modes of P0, P1, P2, P1.ss and P1.cpm
  • Supports fully adaptive channel equalization
  • Built-in self-test feature producing and checking PRBS random pattern

Block Diagram

PCIe 5.0/6.0 PHY IP block diagram

Specifications

Identity

Part Number
PCIe 5.0/6.0 PHY IP
Vendor
Qualitas Semiconductor
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Qualitas Semiconductor
HQ: South Korea
Contact Qualitas Semiconductor

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe Gen5/6 PHY IP?

PCIe Gen5/6 PHY IP is a Multi-Protocol PHY IP core from Qualitas Semiconductor listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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