UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
Vendor:
gSOC Solutions
Category:
Protocol Bridge
AXI2AXI encryption bridge
The PLUG module is a silicon-proven AXI-to-AXI bridge designed to provide data encryption and inline ECC for reliable and secure …
Overview
The PLUG module is a silicon-proven AXI-to-AXI bridge designed to provide data encryption and inline ECC for reliable and secure communication. It supports AXI4 protocol with bursts and integrates seamlessly into systems handling DMA, CPU, or cache streams. For write transactions, it encrypts data and appends ECC, while for reads, it decrypts and validates/corrects ECC. The module is configurable via an APB slave interface and supports both 64-bit and byte-based operations with flexible memory management for ECC storage. It ensures robust error handling, low latency, and compatibility with external memories like Hyper-RAM.
Key features
- Encryption: Implements 64-bit XTEA with dual keys and full 64-round pipelining for security.
- Inline ECC: Embeds ECC into the data stream .
- Dual Operation Modes: Supports both 64-bit whole word and byte-based encryption/ECC.
- Configurable Regions: Allows up to eight address ranges with customizable ECC, encryption, and operational modes.
- Memory Management: Offers separate ECC storage or 8-9 mode for embedding ECC directly into memory.
- AXI Protocol Support: Fully supports AXI4 protocol with burst transactions ( 64bit data bus ).
- Internal configuration registers: accessed through APB slave
- Error Correction: Provides single error correction and double error detection (SEC-DED ECC).
- Interrupts and Safety: Tracks violations and errors with lock-protected safety registers and interrupt mechanisms.
- Split/Merge Mechanism: Handles 4K boundary crossings for seamless burst transfers.
Block Diagram
AXI2AXI encryption bridge block diagram
Specifications
Identity
Part Number
AXI2AXI encryption bridge
Vendor
gSOC Solutions
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Protocol Bridge IP core
Script/simulation approach speeds SoC verification
Script/simulation approach speeds SoC verification
A comparison of Network-on-Chip and Busses
This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures
Synthesizable verification IP speeds design cycle
Synthesizable verification IP speeds design cycle
Synthesizable Verification IP
Synthesizable Verification IP
IP Core for an H.264 Decoder SoC
This paper presents the development of an IP core for an H.264 decoder. This state-of-the-art video compression standard contributes to reduce the huge demand for bandwidth and storage of multimedia applications. The IP is CoreConnect compliant and implements the modules with high performance constraints.
Frequently asked questions about Protocol Bridge IP cores
What is AXI2AXI encryption bridge?
AXI2AXI encryption bridge is a Protocol Bridge IP core from gSOC Solutions listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.