ETSI SSP I3C Interface
The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Comm…
Overview
The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Common Layer (SCL) protocol. The use of the MIPI I3C Basic bus specification provides the ETSI SSP with a multitude of benefits, such as higher data rate, flexible and efficient information exchange, and strong integration of SSP in connected devices. The ETSI SSP is a highly secure, scalable and cost-efficient.
Key features
- The main MIPI I3C features used in the ETSI specification
- IBI support with payload
- Single Data Rate
- Power management
- Power saving mode
- Operating voltages
- Dynamic Addressing
- CCC commands Broadcast and Direct
- Hot-join (in case of removable SSP TBD)
- The SSP features in I3C
- The SSP is Target Only
- One SSP per system
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about I2C / I3C IP core
Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
MIPI I3C v1.1 - A Conversation with Ken Foust
How to Connect Sensors with I3C
MIPI CCI over I3C: Faster Camera Control for SoC Architects
Arasan I3C PHY - Ternary vs. Non-Ternary
Frequently asked questions about I2C / I3C IP cores
What is ETSI SSP I3C Interface?
ETSI SSP I3C Interface is a I2C / I3C IP core from MAXVY Technologies Pvt Ltd listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.