Vendor: Signature IP Corporation Category: CXL

CXL 3.0 Subsystem

Controller + ATC + ATS + DTI · CXL.io · CXL.cache · CXL.mem · Memory pooling

Overview

CXL 3.0 solution with memory pooling and back-invalidation. Shared ATC/ATS/DTI architecture with PCIe Gen 6: one NoC attachment point for both protocols. Type 1/2/3, memory pooling, back-invalidation.

 

Key specifications

CXL version 3.0 / 3.2
Sub-protocols CXL.io · cache · mem
ATC/ATS Pre-integrated
Device types Type 1 / 2 / 3
Memory pooling Multi-host CXL 3.x
DTI boundary Shared with PCIe

Technical details

Physical layer PCIe Gen 6 (shared SerDes (partner))
Back-invalidation CXL 3.x supported
Coherency CXL.cache full protocol
Consortium CXL Consortium member
Sign-off Siemens Questa
Silicon IO silicon

Key features

  • CXL.io · CXL.cache · CXL.mem
  • Shared DTI with PCIe subsystem
  • Type 1 / 2 / 3 device support
  • Multi-host memory pooling (CXL 3.x)
  • CXL Consortium member

Block Diagram

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Specifications

Identity

Part Number
CXL 3.0 Subsystem
Vendor
Signature IP Corporation
Type
Silicon IP

Provider

Frequently asked questions about CXL IP cores

What is CXL 3.0 Subsystem?

CXL 3.0 Subsystem is a CXL IP core from Signature IP Corporation listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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