UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express and CXL. The IP enables latency-optimized NoC-to-NoC links with AXI, CXS, CHI C2C, and streaming protocols. The controller IP implements an RDI interface to the PHY and an FDI interface between the Die-to-Die Adapter and Protocol Layers. These interfaces include all the necessary sideband signaling for protocol discovery and negotiation between two dies, and smooth link initialization and operation. The UCIe Controller IP offers maximum performance, minimum latency, and implementation flexibility. The IP ensures link reliability by supporting retry mechanism and performing CRC or parity checks for error detection. The flexible IP implementation targets single-module or multimodule configurations, both for advanced and standard packages. The UCIe Controller IP along with the UCIe PHY IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die designs. The UCIe Controller IP along with the UCIe PHY IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die designs.

• Low latency controller for UCIe-based multi-die designs
• Includes Die-to-Die Adapter layer and Protocol layer
• Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
• Error detection and correction with optional CRC and retry functionality
• Supports single-module and multi-module UCIe configurations