Scale-Up Ethernet Ecosystem Ramps Up: Cadence ESUN Controller IP Available
Building on its High-Speed Ethernet controller IP family, Cadence provides ESUN-ready controller IP for next-generation AI scale-up networking.
Vendor:
T2M GmbH
Category:
Ethernet
D-MAC-10/100
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
Overview
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to IEEE 802.3 standard.
Key features
- Conforms to IEEE 802.3-2002 specification
- Configurable width CPU interface with little or big endianess:
- 8-bit
- 16-bit
- 32-bit
- Simple interface allows easy connection to CPU
- Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
- Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
- Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
- Supports full and half duplex operation at 10 Mbps or 100 Mbps
- CRC-32 algorithm:
- calculates the FCS nibble at a time
- automatic FCS generation and checking
- able to capture frames with CRC errors if required
- Dynamic PHY configuration by STA management interface
- Early receive and transmit interrupts to increase data throughput
- Programmable MAC address
- Promiscuous mode support
- Allows operation from a wide range of input bus clock frequencies
- Fully synthesizable
- Static synchronous design
- Positive edge clocking
- No internal tri-states
- Lite design, small gate count and fast operation
- Scan test ready
Block Diagram
D-MAC-10/100 block diagram
Applications
- Embedded microprocessor boards
- Networking devices (Network Interface Cards, routers, switches)
- Communication systems
Specifications
Identity
Part Number
D-MAC-10/100
Vendor
T2M GmbH
Type
Silicon IP
Provider
HQ:
Germany
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Frequently asked questions about Ethernet IP cores
What is D-MAC-10/100?
D-MAC-10/100 is a Ethernet IP core from T2M GmbH listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.