I2C Controller IP – Slave, Parameterized FIFO, AXI Bus

The DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 4/3 AXI System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.

The DB-I2C-S-AXI is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices. Figure 1 depicts the system view of the DB I2C-S-AXI Controller IP Core embedded within an integrated circuit device.

The DB-I2C-S-AXI Controller IP Core targets embedded processor applications with higher performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-S-AXI contains a parameterized FIFO and Finite State Machine control for the processor to off-load the I2C transfer to the DB I2C-M-AXI Controller. Thus, while the DB-I2C-S-AXI is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks. Note that the Slave only capability of the DB-I2C-S-AXI adds to its small VLSI footprint requirements.

The DB-I2C-S-AXI supports AXI4-Lite, AXI4, AXI3 AMBA specifications.

The DB-I2C-S-AXI could be paired with the DB-I2C-M-AXI or DB-I2C-MS-AXI in another ASIC/ASSP/FPGA, for robust & VLSI efficient transfer of blocks of data.

• Slave I2C Controller Modes:
  • Slave – Transmitter
  • Slave – Receiver
• Supports four I2C bus speeds:
  • Hs-Mode (3.4+ Mb/s)
  • Fast Mode Plus (1 Mbit/s)
  • Fast Mode (400 Kb/s)
  • Standard Mode (100 Kb/s)
  • Ultra Fast-mode (5 Mbit/s)
• Parameterized FIFO memory for off-loading the I2C transfers from the processor:
  • Targets embedded processors with higher performance algorithm requirements, by the I2C Controller independently controlling theTransmit or Receive of bytes of information buffered to and from a FIFO.
• I2C compliant features:
  • Repeated Start, 7/10-bit addressing, General Call Addressing, & SCL Low Wait States
• Enhanced system-level features & integration capabilities:
  • CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon interconnect fabrics
  • Enhanced SCL / SDA spike filtering capabilities
  • Enhanced Repeated Start capabilities
• Enhanced system-level features & integration capabilities (OPTIONAL):
  • DMA transfer between the I2C Bus & Memory (SDRAM / SRAM / FLASH)
  • Direct interface to user Registers within ASIC / ASSP / FPGA device, for Master/Slave transfer across the I2C Bus
  • Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
• 8 sources of internal interrupts with masking control
• Compliance with AMBA 3/4 and I2C specifications:
  • AMBA Specification (Rev 3/4), AXI4, AXI4-Lite, AXI3 Bus
  • Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and UM10204 Rev 7 – 1 Oct 2021
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASICdesign flows.

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.