Overview
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The core is also suitable for implementing controllers for the Power Management Bus (PMBUS).
The core can be programmed to operate either as a bus master or a slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master/slow-slave communication. Furthermore, the core detects timeout and errors to prevent bus deadlocks, and can filter out glitches on the serial line. The control, status, and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.
The I2C-SMBUS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design uses rising-edge-triggered flip-flops only with the reset type (i.e. asynchronous and/or synchronous) being configurable at synthesis time. Furthermore, the core does not use tri-states; therefore scan insertion is straightforward.
Learn more about I2C / I3C IP core
The I2C (Inter-Integrated Circuit) Bus invented in 1980 by Philips Semiconductors (NXP Semiconductors today) was a massive step forward in simplifying communications in embedded systems. It is a simple two-wire interface for synchronous, multi-master/multi-slave, single ended serial communication. Fast forward 45 years to today and it is still widely used for attaching low speed peripheral Integrated Circuits (ICs), processors and microcontrollers. But silicon today has changed...
Early in my career selling chips for Motorola Semiconductor, the ability to spin derivative microcontroller chips for a customer’s specific requirement was relatively straightforward. If the volume looked reasonable, we would tape-out a new chip with a few added features because mask costs and wafers were relatively inexpensive at the larger process nodes. The customer won by getting an MCU tailored to their specific need, and Motorola won by gaining a more committed customer plus another SKU that could be sold to other customers – boosting ROI. With the migration to higher cost FinFET nodes, those times are long gone as the economics no longer work.
Sharmion Kerley, MIPI Director of Marketing and Membership
Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.
