Multi-Channel Flex DMA IP Core for PCI Express

The Multi-Channel DMA IP Core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces. Up to 16 independent AXI Stream Slaves write DMA Data to the Host. Up to 16 AXI Stream Masters read DMA Data from the Host and present it to the User Logic. Each channel operates on a separate memory area. Additional 8 AXI4 Masters are available to interface full AXI or AXI-Lite peripherals with the Host.

Due to a powerful arbitration scheme, it is possible to control the priority of each DMA channel over other active channels. The link stability detector module measures the signal integrity of the PCI Express Link for lab or production tests to prevent shipments of faulty devices.

This IP Core enables the developer to build complex PCI Express endpoints with no specific PCI Express protocol know how. The user only transmits/receives payload data and does not have to build valid PCI Express packets.

• Multi-channel architecture
• Non-blocking approach, an incomplete AXI Stream packet does not block other AXI Streams
• Up to 16 AXI Stream Slave interfaces
• Up to 16 AXI Stream Master interfaces
• Up to 8 AXI Masters to interface user registers
• User transmits / receives only user data without PCIe protocol knowledge
• Supports 32-Bit and 64-Bit addressing
• Independent clocking and data width for each AXI Stream interface
• Adjustable priority control
• Memory size up to 4 GByte per streaming channel
• Based on AMD / Altera integrated PCI-Sig compliant PCIe Block (HardIP)
• Link speed Gen 1-3, link widths x1-x8
• Available for all AMD and Altera devices

• Encrypted VHDL or source code
• Comprehensive user guide and app notes
• Reference design
• Windows or Linux driver package
• PCIe test bench with high-speed simulation mode
• Technical support