I2C Master Serial Interface Controller

The I2C_MASTER IP Core is a Philips® I2C compliant serial interface controller capable of driving a standard two-wire bus in single-master mode. The controller receives data and instructions via the master instruction interface. These instructions are then processed by the controller state-machine in order to generate the appropriate responses on the SCL and SDA lines.

Likewise, any slave responses on the I2C-bus are captured by the controller and de-serialized for presentation at the slave read data port.

The I2C master controller is comprised of three main blocks as described by Figure 1. These blocks are the master instruction write FIFO, the I2C controller core and the slave read data FIFO.

The I/O ports SCL and SDA are connected to bi-directional tristate buffers. Note that when the I2C controller is inactive, both the SCL and SDA lines will be tristate and as such, these pins should be externally pulled up as per the I2C specification.

The SCL clock-period is determined by the the generic parameter: t_period. This parameter specifies the SCL period in system clock cycles. As an example, if the system clock 'clk' is running at 100MHz and an SCL clock frequency of 100kHz is required (I2C standard mode), a value of t_period = 1000 should be specified.

In addition, the generic parameter t_data_su permits the SDA data-line to be delayed by 'n' system clock cycles relative to the SCL line. In this way, the SDA setup and hold specification can be modified accordingly.

• Technology independent IP Core for FPGA and ASIC
• Supplied as human readable VHDL (or Verilog) source code
• Phillips® I2C-bus compliant
• Intuitive command interface featuring a simple valid-ready handshake protocol
• Master instruction FIFO permits buffering of sequential I2C requests
• Slave read FIFO permits buffering of slave read data and slave responses
• Fully configurable clocking allows Standard (100 kHz), Fast (400 kHz) custom data rates exceeding 20 MHz
• Configurable setup and hold times on the SDA line relative to the SCL line
• Supports standard 8-bit and 10-bit addressing modes

• Driving I2C slave devices
• Inter-chip board-level communications
• Standard 2-wire comms between a wide range of I2C peripherals, micro-controllers and COTs ICs