Vendor: MAXVY Technologies Pvt Ltd Category: MIPI

MIPI DSI DisplayTransmitter IP

MIPI DSI Transmitter IP is designed to transmit the data to the host processor.

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Overview

MIPI DSI Transmitter IP is designed to transmit the data to the host processor. The MIPI DSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices.

Key features

  • Compliance as per MIPI-DSI-2 version2.0
  • Compliance with C-PHY version 2.0 for DSI-2 Version-2
  • Compliance with D-PHY version 1.2 for DSI-2 Version-2.0
  • Compliance with D-PHY version 2.0 for DSI-2 Version-2.0
  • Compliance with D-PHY version 3.0 for DSI-2 Version-2.0
  • Compliance with MIPI SDF specification
  • Compliance with DBI-2 and DPI-2
  • DSI-2 Transmitter supports Pixel to Byte conversion from Application layer to LLP layer
  • DSI-2 Transmitter compliant peripherals support either of two modes: Command Mode and Video Mode
  • DSI-2 operates in continuous clock behaviour in clock lane when implemented in D-PHY physical layer
  • DSI-2 Transmitter provides the de-skew sequence pattern for video mode support
  • DSI-2 Transmitter supports Lane Distribution Function which accepts a sequence of packet bytes from Low Level Protocol and distributes them across N-Lanes where each lane is independent of PHY layer
  • DSI-2 Transmitter can connect two, three, or four DSI Receivers by splitting the DSI Link (split Link) with DSI Sub-Links for either D Option or C Option
  • DSI-2 Transmitter supports HS mode and Escape mode for transmission of Packets in both C-PHY and D-PHY
  • DSI-2 Transmitter supports symbol slip detection code and sync symbol insertion while operating in C-PHY physical layer
  • DSI-2 Transmitter will insert the Filler bytes in LLP layer in conjunction with C-PHY physical layer to ensure that packet footer ends with 16-bit word boundary
  • DSI-2 Transmitter is used to scramble the data payload and packet footer
  • DSI-2 Transmitter supports C-PHY/D-PHY. Only one PHY layer can be configured at a time of transmission
  • Processor Interfaces are AHB-Lite/ APB/ AXI for configuration

Block Diagram

MIPI DSI-2 TRANSMITTER IP block diagram

What’s Included?

  • Verilog Source Code
  • User Guide
  • IP Integration Guide
  • Run and Synthesis Script
  • Encrypted Verification Test-bench Environment
  • Basic Test-suite

Specifications

Identity

Part Number
MIPI DSI-2 TRANSMITTER IP
Vendor
MAXVY Technologies Pvt Ltd
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact MAXVY Technologies Pvt Ltd

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Frequently asked questions about MIPI IP cores

What is MIPI DSI DisplayTransmitter IP?

MIPI DSI DisplayTransmitter IP is a MIPI IP core from MAXVY Technologies Pvt Ltd listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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