Vendor: Synopsys, Inc. Category: Single-Protocol PHY

USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)

The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.

USB 3.1 TSMC 16nm View all specifications

Overview

The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offering consists of Host, Device, and Dual-Role Device controllers, PHYs with and without support for the USB Type-C™ connectivity specification and DisplayPort 1.3 support, verification IP, IP Prototyping Kits, and IP software development kits. These elements enable quick development of advanced chip designs incorporating the 10 Gbps SuperSpeed USB standard. The Synopsys USB 3.1 IP is targeted for integration into SoCs for media storage, creation, and playback devices, requiring faster bandwidth between PCs and portable electronic devices. Optimized for low power, the Synopsys USB 3.1 Controller and PHY IP allow designers to maximize power efficiency for extended battery life. The Synopsys USB 3.1 IP enables the fastest SuperSpeed USB data transfer speeds while lowering overall power consumption. As the leading supplier of USB IP, Synopsys provides designers with a high-performance, low-power, and area-efficient IP solution, for cost-effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB enables us to build a low risk, high quality SuperSpeed USB IP solution.

Key features

  • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
  • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
  • Configurable data buffering options to optimize performance vs area
  • Supports all USB speed modes
  • Host, Device, and Dual Role Device controllers meet the needs for all markets
  • USB-C 3.1 DisplayPort 1.3 TX Controller includes HDCP 2.2 content protection

Benefits

  • Supports SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps, and High-speed USB (USB 2.0) Optimized Host, Device, and DualRole Device controller IP designed to achieve lowest power and area for portable electronics
  • Synopsys USB-C 3.1/DisplayPort 1.3 TX PHYs and controllers offer high-performance throughput for 4K and 8K display
  • Supports PIPE and UTMI+ PHY interfaces
  • Architectural features reduce power consumption
  • Complete Synopsys USB solutions for USB 3.1 consist of controllers, PHYs, verification IP, IP Prototyping Kits, and IP Software Development Kits
  • SuperSpeed USB IP offering from the #1 provider of USB IP for thirteen years in a row (Gartner 2014)

Applications

  • Synopsys coreConsultant tool
  • Verilog RTL source code
  • ASIC and FPGA synthesis, ATPG, DFT, power scripts
  • UVM Testbench with native SystemVerilog Verification IP for USB
  • Comprehensive databook and integration guides
  • Reference drivers to speed development
  • USB-C 3.1 DisplayPort 1.3 TX Controller includes HDCP 2.2 firmware and host API library SDK

What’s Included?

  • Synopsys coreConsultant tool
  • Verilog RTL source code
  • ASIC and FPGA synthesis, ATPG, DFT, power scripts
  • UVM Testbench with native SystemVerilog Verification IP for USB
  • Comprehensive databook and integration guides
  • Reference drivers to speed development
  • USB-C 3.1 DisplayPort 1.3 TX Controller includes HDCP 2.2 firmware and host API library SDK

Silicon Options

Foundry Node Process Maturity
TSMC 16nm 16nm 160 nm —

Specifications

Identity

Part Number
dwc_usbc31sspphy_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.1

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)?

USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A) is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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