95 dB of SNR, 24-bit audio CODEC with headphone output and line-out
SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording perform…
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS
Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
Quad 3.125/6.25 Gbps Backplane SerDes
IP
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
Single-carrier RF transceiver on TSMC 22nm ULL
Single-carrier RF transceiver on TSMC 22nm ULL
Multi-carrier RF transceiver on TSMC 22nm ULL
Multi-carrier RF transceiver on TSMC 22nm ULL
Integer-N PLL, 800M-3.2G on TSMC 12nm
This present IP is a charge-pump Phase Locked Loop (PLL) circuit, which can cover 800MHz-3200MHz vco output frequency.
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
Specialed 20V Analog I/O in TSMC 55nm
A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS This silicon-proven TSMC 55nm LP 20V ESD cell is a high-vo…
TSMC 3nm HBM3-8.6G PHY
TSMC 5nm HBM3-8.4G PHY
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
TSMC 16nm Thermal Sensor ADC