Linear regulator with ultra low quiescent current for retention applications
The qLR-Aubrey-ref-[1.9-4.4]-[1.2-3.3].01 is an ultra-low-quiescent-current regulator used to generate SoC internal supply for re…
Dolphin Design offer a Reusable Power Kit Library toward three objectives: To standardize and ease Power Regulation Network integ…
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF, SESAME HD DV provides the best trade-off between area and power achieved from an cell design en…
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, SESAME HD DV provides the best trade-off between area and power achieved from an cell design enab…
9 track standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, Sesame 9T, a unique architecture based on 9-track cells, optimized for High Density and Low Dynam…
9 track standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF Sesame 9T a unique architecture based on 9-track cells, optimized for High Density and Low Dynam…
Linear Regulator, ultra low quiescent current for retention mode
qLR-Aubrey-ref-[1.62-3.63]-[0.55-2.5]-I1-Iq150.02, as any Power Management Virtual Component designed by Dolphin Design, is readi…
Comparator with low-quiescent Hysteresis
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Comparator with low-quiescent Hysteresis
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily ret…
Linear Regulator, low quiescent current
The LRA-2.97-3.63-1.8 is a low noise linear regulator.
Linear Regulator, low quiescent current
The LRA-2.97-3.63-1.8 is a low noise linear regulator.
Switching regulator, inductor-based, in dual mode (PFM and PWM) & high efficiency
eSR-Niagara-Bu-dm-ref-[1.62-3.63]-[0.8-2.5].01, as any Power Management Virtual Component designed by Dolphin Design, is readily …
SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)
The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both sing…
12bits 50MS/s pipeline ADC - TSMC 0.18um
12bits 50MS/s pipeline ADC
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latc…
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an cell design ena…