MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification.
- MIPI D-PHY
- TSMC
- 28nm
- HPC+
- In Production
MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption.
Linear Low-Dropout Regulator (Output Voltage 0.6V)
1-VIA’s VSCOM4L400ALDO0V6 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulatio…
Linear Low-Dropout Regulator (Output Voltage 0.9V)
1-VIA’s VSCOM4L400ALDO0V9 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulatio…
4.4 GHz To 7.75 GHz Low phase Noise Fractional-N Synthesizer
The WEA48S55T is a broadband fractional–N frequency synthesizer with integrated phase sync function.
Bandgap Voltage Reference (0.6V and 0.8V References)
1-VIA’s VSCOM4l400ABG IP is a 1.8V low-noise unbuffered programmable 0.6 and 0.8V Bandgap Voltage References (BGR) with eight 50u…
256x8 Bits OTP (One-Time Programmable) IP, TSMC 40G 0.9/1.8V Process
The AT256X8T40G6AA is organized as 256 bits by 8 one-time programmable (OTP).
256x8 Bits OTP (One-Time Programmable) IP, TSMC 22ULP 0.8V/1.8V process
The AT256X8T22ULP6AA is organized as 256 bits by 8 one-time programmable (OTP).
4Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP).
1x64 Bits OTP (One-Time Programmable) IP, TSMC 0.18um Mixed-Signal 1.8V/3.3V Process
The AT1X64T180MM0AB is organized as one by 64 bits one-time programmable (OTP).
Fractional-N Frequency Synthesizer (40nm - 110nm)
The Fractional-N Frequency Synthesizers generate a stable clock from low frequency reference clock.
High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)
The High Stability Oscillators generate 150MHz - 160MHz output frequency with an accuracy of +/-2% or +/-3% or +/-5%.
DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput.
The Integer PLLs generate a stable clock from low frequency reference clock.
PPA optimized for short reach connectivity
1.8GHz SSCG PLL on TSMC 28nm HPC+
Analog-PLL For Spread Spectrum Clock on TSMC 28nm HPC+
ultra Low power Bluetooth v5.3 Dual-Mode RF IP in TSMC40nm
Ultra-Low-Power Bluetooth Dual-Mode RF Transceiver IP in TSMC 40nm Logic LP processes node, The Radio Support standards like Blue…
TSMC 180nm 5V Bandgap
1Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
The AT1K32T40ULP6AA is organized as a 1K-bit by 32 one-time programmable (OTP).