Vendor: Megachips Corporation Category: Oscillator

High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)

The High Stability Oscillators generate 150MHz - 160MHz output frequency with an accuracy of +/-2% or +/-3% or +/-5%.

TSMC 40nm ULP In Production View all specifications

Overview

The High Stability Oscillators generate 150MHz - 160MHz output frequency with an accuracy of +/-2% or +/-3% or +/-5%.
The oscillators need trimming, and stable power supply.
Have mass production results at each technology node.

Key features

High accuracy +/-2%, +/-3%, +/-5% at Tj = -40C to +125C.
The frequency can be adjusted from 150MHz to 160MHz.
Reference clock is not required.
Need to use trimming.
The +/-2% version requires both a stable IO voltage and a core voltage.
The +/-3% version requires only a stable core voltage at TSMC 40nm (CLN40ULP).
The +/-5% version requires only a stable core voltage at UMC 55nm (LP).
As an option, we can provide the eFuse-wrapper for trimming. In this case, the trimming resource is fixed to TSMC/UMC eFuse.

Applications

General Purpose

What’s Included?

GDSII
CDL netlist
Verilog model
Synopsys synthesis model
LEF
User Guidelines

Silicon Options

Foundry	Node	Process	Maturity
TSMC	40nm	ULP	In Production

Specifications

Identity

Part Number

MCC-HSOSC

Vendor

Megachips Corporation

Type

Silicon IP

Provider

Megachips Corporation

HQ: Japan

Frequently asked questions about Oscillator IP cores

What is High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)?

High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP) is a Oscillator IP core from Megachips Corporation listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Oscillator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Oscillator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.