Fractional-N Frequency Synthesizer (40nm - 110nm)
The Fractional-N Frequency Synthesizers generate a stable clock from low frequency reference clock.
High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)
The High Stability Oscillators generate 150MHz - 160MHz output frequency with an accuracy of +/-2% or +/-3% or +/-5%.
DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput.
The Integer PLLs generate a stable clock from low frequency reference clock.
PPA optimized for short reach connectivity
ultra Low power Bluetooth v5.3 Dual-Mode RF IP in TSMC40nm
Ultra-Low-Power Bluetooth Dual-Mode RF Transceiver IP in TSMC 40nm Logic LP processes node, The Radio Support standards like Blue…
TSMC 180nm 5V Bandgap
1Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
The AT1K32T40ULP6AA is organized as a 1K-bit by 32 one-time programmable (OTP).
256x8 Bits OTP (One-Time Programmable) IP, TSMC 0.13um 1.5V/3.3V LP Process
The AT256X8T130LP0AA is organized as a 256-bit by 8 one-time programmable (OTP).
The ATO00256X1TS180MSG3NA is organized as a 256 bit by 1 one-time programmable (OTP).This is a kind of non-volatile memory fabric…
TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple …
DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
This PHY IP supports both USB 3.1 Gen1 & Gen2.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PC…
DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
The DDR4/ DDR3L/ LPDDR4 Combo PHY IP provides low latency and enables up to 3200Mbps throughput.
In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring, TSMC 28HPC+
A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a subsystem dedicated to max…
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
PCIe is the most common protocol in high speed serial standards to connect components in embedded systems.
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The Combo PHY is a USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process.