Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
3.125 Gbps DDR 1-channel CML transmitter
065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to …
065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin E…
Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet …
ESD diode and Clamps for 90nm TSMC G/GT/LP
Stand alone ESD diodes and Supply clamping for TSMC 90nm G/GT/LP processes
TSMC 22nm 1.0V, 1.2V & 1.8V GPIO
Overvoltage tolerant design - Supports multiple supply voltages - Input enable/disable
TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
This TSMC 3nm 1.8V, 1.2V and 0.9V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins.
TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins.
TSMC 22nm 5V5 ESD Power Clamp – Low Leakage
This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins.
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs.
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 12nm 0V8 ESD Local Protection Low Cap
This TSMC 12nm 0.8V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.
This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs.
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
The TSMC 2nm 1.2V GPIO offers configurable I/O functionality with multi-voltage support, over-voltage tolerance (OVT), and high-speed or ultra-low-power modes.
SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Silicon-proven ESD protection for GAA/nanosheet technologies
TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
Silicon-proven ESD protection for GAA/nanosheet technologies