Vendor:
Sofics
Category:
ESD Protection
TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
Overview
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This ESD protection IP provides robust on-chip protection for sensitive I/O and interface pins while minimizing impact on signal performance, leakage, and silicon area. The solution is designed for integration in multiple process nodes and can be adapted to specific interface requirements, voltage domains, and foundry design rules.
The protection concept supports reliable operation under HBM and CDM stress conditions and can be customized for higher robustness levels, low-capacitance interfaces, low-leakage applications, or reduced-area.
Details
| Parameter | Value |
|---|---|
| VDD | 3.3V ±10% |
| VDDIO | VDD+0.3V ±10% |
| Temperature Tj | -55C to 125C |
Key Features
| Parameter | Value |
|---|---|
| TLP | 1.33A |
| HBM | 2kV |
| CDM | 500V |
| Leakage | <1nA |
| Capacitance | 231fF |
| TID | >1 MGy |
| SEE | 80 MeV·cm²/mg |
Area
| Type | Size [μm²] |
|---|---|
| ESD Clamp | 1652.31 |
Key features
- Local protection for I/O / analog / RF pins
- Supports HBM and CDM robustness targets
- Low-capacitance implementation
- Low-leakage options available
- Compact ESD clamp layout
- Compatible with foundry or custom pad ring integration
Block Diagram
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Benefits
- Silicon-proven ESD protection for CMOS technologies
- High robustness against HBM, CDM, latch-up and system-level stress conditions
- Low parasitic capacitance
- Compact layout footprint compared to conventional foundry ESD solutions
- Customizable trigger, holding voltage, leakage and clamp configuration
- Modular design enables fast and reliable turnaround and low NRE
- Radiation hard design for excessive radiation environments
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | LP | Available on request |
Specifications
Identity
Part Number
DS-TS65N-3V3-LC-LWC-RH-ESD
Vendor
Sofics
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Belgium
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Frequently asked questions about ESD Protection Library IP cores
What is TSMC 65nm 3V3 ESD Local Clamp – Rad Hard?
TSMC 65nm 3V3 ESD Local Clamp – Rad Hard is a ESD Protection IP core from Sofics listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this ESD Protection?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.