Vendor: Certus Semiconductor Category: Analog

IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes

Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet …

TSMC 28nm View all specifications

Overview

Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet offerings. Our I/O solutions include 1.8V & 3.3V GPIO, I2C, SMBUS, open-drain, RGMII, SD, LVDS, HDMI and more.
Drawing from this rich database, Certus has a starting point from which we can create any custom additions you may need. Our building-block design style also enables us to configure our IOs to fit a variety of cell sizes, aspect ratios, pad arrangements and packages. We work closely with our clients to provide tailored solutions affordably and with fast turnaround.

Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we address standard ESD such as HBM and CDM, but we can also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).

Key features

  • Certus offers dedicated 1.8V, 3.3V and switchable 1.8V/3.3V General-Purpose IO (GPIO) solutions.
  • GPIO features include:
    • Dedicated 1.8V & 3.3V cells or dynamically switchable 1.8V/3.3V cell
    • Multiple drive strengths (dedicated cells or selectable)
    • Supply sequence independence
    • Output enable / disable (HiZ when disabled)
    • Schmitt trigger input
    • Selectable pull-up or pull-down resistor
    • Flexible metal stack and cell pitch variations
    • Wirebond & Flip-Chip support
  • I2C / SMBUS Open-Drain I/O features include:
    • Up to 5V external supply support
    • Hysteresis input
    • Power sequence independence
    • External resistor support of 1K-50K Ohm
    • Fail-safe protection
    • 2KV HBM, 500V CDM
    • Also DDC, CEC and HPD compliant
  • LVDS I/O features include:
    • Output enable (TX)
    • Input enable (RX)
    • Internally generated common mode reference (no external pin required)
    • Built-in 100? RX termination resistor
    • Fault-safe mode for shorted or open RX pins
    • Power-on sequence independence
    • ESD protection of 2KV HBM, 500V CDM

Block Diagram

Certus IO Libraries block diagram

Benefits

  • High confidence level for first time-right IC ESD design backed by SPICE simulation, optimization and verification methodology including HBM & CDM specifications
  • Highly area-efficient solutions allowing for IO height reductions of typically > 20% compared to standard foundry IOs
  • Portable & foundry proven
  • Si product proven IP in most advanced CMOS from 180nm down to 12nm
  • Uniform ESD protection levels with more effective CDM protection
  • Standard, full custom libraries plus IO template library offering
  • Fast turnaround custom IO library designs

What’s Included?

  • GDS
  • CDL netlist
  • Verilog stub
  • Verilog behavioral model
  • LEF
  • Liberty Timing Files
  • IBIS (option)
  • Electrical datasheet
  • User guide and application notes
  • Consulting and Support

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm —

Specifications

Identity

Part Number
Certus IO Libraries
Vendor
Certus Semiconductor
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Certus Semiconductor
HQ: United States

Learn more about Analog IP core

CDM Dependence on Device Capacitance

This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.

Field Induced CDM Explained

Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.

One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

Frequently asked questions about Analog I/O Pad Library IP cores

What is IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes?

IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes is a Analog IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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