Vendor: Sofics Category: ESD Protection

TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap

This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

TSMC 7nm N7+ Available on request View all specifications

Overview

This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow. Multiple clamp variants enable trade-offs between ESD robustness, parasitic capacitance, leakage and silicon area, including options down to 10fF capacitance and 133.84µm² area.

This ESD protection IP provides robust on-chip protection for sensitive I/O, supply, and interface pins while minimizing impact on signal performance, leakage, and silicon area. The solution is designed for integration in multiple process nodes and can be adapted to specific interface requirements, voltage domains, and foundry design rules.

The protection concept supports reliable operation under HBM and CDM stress conditions and can be customized for higher robustness levels, low-capacitance interfaces, low-leakage applications, or reduced-area.

Details

Parameter Value
VDD 0.75V ±10% | 0.9V ±10%
Temperature Tj -40C to 25C

Example Set of Clamps

Type HBM Target Leakage Capacitance [fF] Area [µm²]
High ESD, low-cap 1kV HBM 200pA at 125C 48 401.45
Lower area, low-cap 1kV HBM 200pA at 125C 48 323.65
Ultra-low cap / small area 100V HBM 50pA at 125C 14.3 156.62
Lowest cap / lowest area 80V HBM 50pA at 125C 10 133.84

 

Key features

  • Local protection for I/O / analog / RF pins
  • Supports HBM and CDM robustness targets
  • Low-capacitance implementation
  • Low-leakage options available
  • Compact ESD clamp layout
  • Compatible with foundry or custom pad ring integration

Block Diagram

Click to open fullscreen

Benefits

  • Silicon-proven ESD protection for FinFET technologies
  • High robustness against HBM, CDM, latch-up and system-level stress conditions
  • Low parasitic capacitance
  • Compact layout footprint compared to conventional foundry ESD solutions
  • Customizable trigger, holding voltage, leakage and clamp configuration
  • Modular design enables fast and reliable turnaround and low NRE

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Available on request

Specifications

Identity

Part Number
DS-TS7N-0V75-LC-ESD
Vendor
Sofics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Sofics
HQ: Belgium

Learn more about ESD Protection IP core

EOS protection characterization using Long-Pulse TLP

EOS, or Electrical Overstress, is a significant factor in IC reliability. Sometimes, IC interfaces and/or power pads are subjected to voltage/current levels beyond the absolute maximum rating. Sources claim that more than 40% of the field failures in electronic products are related to EOS.

Frequently asked questions about ESD Protection Library IP cores

What is TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap?

TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap is a ESD Protection IP core from Sofics listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this ESD Protection?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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