Overview
This specific IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This ESD protection IP provides robust on-chip protection for sensitive supply, and interface pins while minimizing impact on signal performance, leakage, and silicon area. The solution is designed for integration in multiple process nodes and can be adapted to specific interface requirements, voltage domains, and foundry design rules.
The protection concept supports reliable operation under HBM and CDM stress conditions and can be customized for higher robustness levels, low-capacitance interfaces, low-leakage applications, or reduced-area.
Details
| Parameter |
Value |
| VDD |
1.8V ±10% |
| Temperature Tj |
-40C to 125C |
Key Features
| Parameter |
Value |
| Leakage |
<14nA |
| TLP |
4.82A |
| HBM |
7.25kV |
| CDM |
13.5A |
Area
| Type |
Size [μm²] |
| Power |
1463.4 |
Learn more about ESD Protection IP core
Most practical photonic systems combine a Photonic Integrated Circuit (PIC), which manipulates photons, with an Electronic Integrated Circuit (EIC) that manipulates electrons. Both types of chips require highly specialized design expertise and dedicated manufacturing processes. Both must also ultimately work together seamlessly. And both can take considerable time and engineering effort to develop from scratch. The best approach for such a design task is to start from proven IP on both sides. Alcyon Photonics and Sofics bring complementary expertise to this challenge.
Specialty I/O topologies, co-designed with robust on-chip ESD protection, give SoC and chiplet designers expanded interface voltage, and I²C options on advanced processes
We joined Siemens EDA, through EDA Solutions in June 2026 for a webinar on why a design that looks perfectly correct on schematic can still fail once it’s extracted from layout, and what that means for specialty I/O verification at advanced nodes.
Most chips live an easy life with room temperature, clean power and a steady supply. The chips in this article do not. They sit inside nuclear reactors, ride on satellites and work next to particle beams, where a single stray particle can corrupt data or destroy a device.
To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.
Collaboration brings together robust ESD protection for electrical ICs and foundry-validated IP for photonic ICs, helping mutual customers accelerate photonics product development.
