Vendor: Sofics Category: ESD Protection

TSMC 12nm 2V5 ESD Power Clamp

This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs.

TSMC 12nm FFC Available on request View all specifications

Overview

 

This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs. It is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

The TSMC 12nm 2.5V ESD Power Clamp provides robust on-chip protection for sensitive supply and interface pins while minimizing impact on signal performance, leakage, and silicon area. The solution can be adapted to specific interface requirements, voltage domains, ESD robustness targets, and foundry design rules.

The protection concept supports reliable operation under HBM and CDM stress conditions and can be customized for higher robustness levels, low-capacitance interfaces, low-leakage applications, or reduced-area.

Details

Parameter Value
VDD 2.5V ±10%
Temperature Tj -40C to 125C

Key Features

Parameter Value
TLP 2.33A
HBM ±3.5kV
Leakage 8nA @ 25C
800nA @ 125C

Area

Type Size [μm²]
Power 2303

Key features

  • Power protection for supply / analog / RF / high-voltage pins
  • Supports HBM and CDM robustness targets
  • Optional support for IEC / EOS / EMC
  • Low-capacitance implementation
  • Low-leakage options available
  • Compact ESD clamp layout
  • Compatible with foundry or custom pad ring integration

Block Diagram

Benefits

  • Silicon-proven ESD protection for FinFET technologies
  • High robustness against HBM, CDM, latch-up and system-level stress conditions
  • Low parasitic capacitance
  • Compact layout footprint compared to conventional foundry ESD solutions
  • Customizable trigger, holding voltage, leakage and clamp configuration
  • Modular design enables fast and reliable turnaround and low NRE

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC Available on request

Specifications

Identity

Part Number
DS-TS12N-2V5-PC-ESD
Vendor
Sofics
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Belgium

Learn more about ESD Protection IP core

EOS protection characterization using Long-Pulse TLP

EOS, or Electrical Overstress, is a significant factor in IC reliability. Sometimes, IC interfaces and/or power pads are subjected to voltage/current levels beyond the absolute maximum rating. Sources claim that more than 40% of the field failures in electronic products are related to EOS.

Frequently asked questions about ESD Protection Library IP cores

What is TSMC 12nm 2V5 ESD Power Clamp?

TSMC 12nm 2V5 ESD Power Clamp is a ESD Protection IP core from Sofics listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this ESD Protection?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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