Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel noise back to the …
- Channel Coding
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel noise back to the …
Lattice's FFT Compiler offers forward and inverse Fast Fourier Transforms for point sizes from 64 to 16384.
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, de…
Single Precision IEEE-754 complete FPU
The A2F is a fully synthesizable module implemented in Verilog RTL.
The CMS0006 Universal QAM Demodulator is a 4th generation design that exploits Commsonic’s experience of QAM and OFDM systems for…
The CMS0004 Universal QAM/PSK Modulator is a flexible, high-performance, linear modulator core designed for a wide range of broad…
The FFT is factored into Radix-4 Butterfly operations.
Reed Solomon Codec (Errors-only)
The CMS0007 Reed Solomon Codec provides ultimate flexibility in its operation and build.
The SI80MC51 is an Intel microcontroller compatible, which is a true computer on chip.
Viterbi encoding is widely used for satellite and other noisy communications channels.
IP-ALIDCT soft core is the unit to perform the Inverse Discrete Cosine Transform (IDCT).
IP-ALDCT soft core is the unit to perform the Discrete Cosine Transform (DCT).
Intel™ 8051 8-bit Microcontroller
The IP-AL8051 core is the VHDL model of the Intel™ 8-bit 8051 micro controller.
The Accumulator IP provides LUT and single DSP48 slice accumulation implementations.
Very High Speed 16 State MAP Decoder
This is a very high speed 16 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder wi…
This is a high speed 16 state maximum a posteriori (MAP) soft-in-soft-out (SISO) error control decoder with log-likelihood-ratio …
Instruction Set Compatible with the 8051 8-bit Microcontroller Architecture
IP-AL8051S soft core is instruction set compatible with the 8051 8-bit microcontroller architecture and can achieve average perfo…
High Performance 8051 Compatible CPU Core
The V805x is a synthesizable VHDL (soft) core design which is object code compatible with Intel's popular 8-bit 8051 microprocess…
Synthesizable 6800 Compatible CPU Core
The V6800 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular 8-bit MC6800 micropr…
Synthesizable 68000 Compatible CPU Core
The V68000 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular MC68000.