The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
- Channel Coding
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
Xilinx provides a market DPD solution that reduces CapEx and OpEx Digital Pre-Distortion (DPD) is one of the most fundamental bui…
The 3GPP LTE Channel Estimator LogiCORE™ IP provides an optimized channel estimation function for the Physical Uplink Shared Chan…
The 3GPP LTE Turbo Encoder implements the turbo convolutional encoding scheme defined in the 3GPP LTE specifications.
The 3GPP LTE RACH Detector offers a flexible and optimized implementation of the RACH detection function required for 3GPP-LTE ba…
3GPP LTE Fast Fourier Transform (LTE-FFT)
The LTE FFT LogiCORE™ IP provides support for all transform point sizes defined by the 3GPP-LTE specifications, including the 153…
Peak Cancellation Crest Factor Reduction (PC-CFR)
Xilinx provides a CFR solution for common wireless standards that is low cost, flexible, low power and solves your time to market…
Xilinx provides a DUC/DDC solution for LTE, TD-SCDMA and WCDMA that is low cost, low power and solves your time to market needs.
The Xilinx LogiCORE™ DSP48 Macro provides an easy-to-use interface that abstracts the DSP48 slice and simplifies its dynamic oper…
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from …
32/64/128/256/512/1024/2048/4096 Point FFT Core
The FFT4096 core the FFT and IFFT computations for N input samples, where N can be any power of 2 between 32 and 4096 (32, 64, 12…
The CMS0041 DVB-T2 Modulator provides all the necessary processing steps to modulate single transport stream into a complex I/Q s…
The LEON4 processor builds on the success of its predecessors, providing enhanced performance and efficiency for demanding space …
The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third ope…
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA.
The Multiply Accumulator IP accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is adde…
Included with Xilinx ISE Software The Multiplier Accumulator IP core product is a parallel multiplier accumulator module that per…
The LTE Baseband Platform enables customers to more easily exploit the advantages of a 100% Xilinx FPGA baseband implementation, …
The LTE MIMO Decoder provides LTE basestations developers with a optimized and scalable MIMO decode function.
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder
TC4300 is a LDPC decoder designed for China Multimedia Mobile Broadcasting (CMMB) specifications.