The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
- Control Logic
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
The flip-flop logic is designed to be used with Platform Studio to perform simple logical operations.
The Bus Split operation is designed to be used with Platform Studio to split a bus into smaller buses.
The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based D…
UMTS/3GPP Turbo Convolutional Encoder
This version of the Turbo Convolutional encoder is designed to meet the 3GPP specification.
The Interleaver/De-interleaver LogiCORE™ module is a high-speed, compact design that is fully synchronous, using a single clock.
The Xilinx LogiCORE™ CORDIC IP implements a generalized coordinate rotational digital computer (CORDIC) algorithm, initially deve…
The Xilinx® LogiCORE™ IP Convolutional Encoder core can be used in a wide variety of error correcting applications and is typical…
The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers…
The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations.
Aliathon’s 2.5Gbps GFP-T Encoder Core provides a flexible, resource-efficient, high-density programmable logic based solution for…
NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications.
Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fa…
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
Dynamic Block Reed-Solomon Encoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Dynamic Block Reed-Solomon Decoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Convolutional encoding is a process of adding redundancy to a signal stream to provide error correction capability.
Turbo coding is an error correction technique widely used in the communications industry.
Turbo coding is an error correction technique widely used in the communications industry.
Distributed Arithmetic FIR (DA-FIR) Filter Generator
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP implements a configurable, multi-channel …