The J5 is a core cell design of an application specific signal processor which performs both Trusurround(TM) and SRS® 3-D audio v…
- DSP Core
- The J5 is available for license immediately.
- SRS, TruSurround
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The J5 is a core cell design of an application specific signal processor which performs both Trusurround(TM) and SRS® 3-D audio v…
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
Compiler-centric single-core LPU
Compiler-centric single-core LPU IP for on-device LLM inference on resource-constrained edge devices.
Purpose-built AI model compression IP, combining software compression with hardware decompression for static model data and hardw…
RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Unlocking AI with Open Compute Traditional AI processors force customers into closed hardware-software ecosystems that limit inno…
Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge
Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge
The NAND Flash landscape is changing and the Arasan NAND flash management technology is changing with it.
The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the sp…
Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
ARC IoT Communications IP Subsystem
IP
RISC-V Vector Extension
RISC-V Real-time Processor
RISC-V High Performance Processor
RISC-V High Performance Processor
RISC-V IP - Dual Issue Power Efficient Application
Dual Issue Power Efficient Application Core - VisionL is a dual-issue power-efficient application core designed for applications …
RISC-V IP - Dual Issue Embedded Application
Dual Issue Embedded Application Core - VisionG is a dual-issue embedded application core, providing high-performance computing ca…
RISC-V IP - Entry Level Application Core
Entry Level Application Core - VisionC is an entry-level application core that strikes the perfect balance between cost-effective…
RISC-V IP - Microcontroller Unit (MCU) level
MCU Level Core - VisionA is our Microcontroller Unit (MCU) level core, offering exceptional versatility and efficiency for embedd…
Ultra-low power RISC-V microcontroller CPU
IP
Revolutionary vector processor
From early Motorola and TI DSPs to modern smartphone DSPs in application processors, DSPs have been designed and optimized for in…