Learn more about Filters Transforms IP core
The update helps engineering teams improve correctness, maintainability, and IP interoperability when combining VHDL and Verilog/SystemVerilog within a single project.
Aldec has updated its popular linting tool ALINT-PRO to enhance the support of Microchip Technology’s Libero® SoC Design Suite. The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, is supporting Open Component Portability Infrastructure (OpenCPI) with the latest release of Riviera-PRO (release version 2022.04).
The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification.
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has helped Thales evaluate the use of transaction-level modeling (TLM) for the verification of a PCIe-based FPGA design requiring DO-254 compliance.
Available through Amazon Web Service (AWS), HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and has a focus on automated design partitioning to greatly reduce bring-up time when up to four FPGAs are needed to accommodate a design.
