Reed Solomon Codec (Errors-only)

The CMS0007 Reed Solomon Codec provides ultimate flexibility in its operation and build. The design uses the Berlekamp Massey algorithm in order to maximise speed and efficiency.

Synthesis Parameters

Setting up the Reed-Solomon codec is very simple. Firstly, it is necessary to set up the Galois field over which the code will operate using three parameters:

• gal_bps. Bits per symbol (typically 7 or 8 for communications applications).
• gal_alpha. Primitive root of the field (usually 2).
• gal_field_gen_poly. Field Generator Polynomial (e.g. x8+x4+x3+x2+1 is usually used for GF{28}. Once the field is set up, the next task is to select the Reed-Solomon code parameters. This involves configuring the parameters:
• RS_T. The number of symbols that can be corrected per codeword.
• J0. The first power of alpha used in the code generator polynomial.

The code polynomial G(x) is then determined by:

G(x) = (1-α^J0) (1-α^J0+1)… (1-α^J0+2*RS_T-1)

These parameters are set once in a VHDL package and are applicable to the full design. The field and code parameters are set by constants and fixed for a particular implementation of the block.

Register Configuration

Once the code has been selected, it is possible to adapt the correcting power for a particular application by adjusting the values of N that is selectable using the register RS_N.

For example, if the code instantiation selected is an RS(255, 239) code then the decoder is capable of correcting eight errors in every 255 symbols - since N=255 and T=8 are the maximum values permitted by this instantiation. Setting RS_N less than 255 will allow the same number of errors to be fixed in a shorter block size thereby increasing the correcting power of the code.

An additional feature is the ability to accept new value on N on a packet-by-packet basis. The value of N is loaded with sync and valid to allow on-the fly changes. Alternatively the value of N may be tied to a constant to minimise gate count.

• Errors Only Reed-Solomon CODEC using the Berlekamp Massey algorithm for efficient implementation.
• Register programmable, fixed or synchronous “on-the-fly” loading for different values of N in a Reed-Solomon (N, N-2T) code. T fixed by synthesis.
• Supports shortened codes.
• Can be synthesised for any Galois Field, Reed-Solomon code, and correcting power T, with maximum values for N set by synthesis parameters.
• Requires one single-port memory with storage for two non-shortened Reed Solomon blocks.
• Excellent performance in both FPGA and ASIC implementations.
• Supplied as vector matched C++ and VHDL source with synthesis scripts for Synopsys DC Ultra‰ and Synplify Pro“.