Vendor: Xilinx, Inc. Category: Arithmetic Units

Complex Multiplier

The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers…

Overview

The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers based on user-specified options. All operands and the results are represented in signed two’s complement format. The operand widths and the result width are parameterizable.

Key features

  • Support AXI4-stream interface
  • Delivers VHDL demonstration testbench with CORE Generator
  • Supports inputs ranging from 8 to 63 bits wide
  • Supports outputs ranging from 1 to 127 bits wide
  • Supports truncation or unbiased rounding.
  • Option to use LUTs or embedded multipliers  DSP48 slice.
  • Optimization for speed or resource utilization is available through implementation using the 3-multiplier or the 4-multiplier solutions
  • Instantaneous Resource Estimation of  DSP48 slice

Specifications

Identity

Part Number
Complex Multiplier
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about Arithmetic Unit IP cores

What is Complex Multiplier?

Complex Multiplier is a Arithmetic Units IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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